The present invention relates to a method for fabricating a semiconductor device, and more particularly to a semiconductor device having a vertical-type channel and a method for fabricating the same.
As the integration scale of semiconductor devices has been increased, an increase in cell electric charges and an improvement in a refresh property have a direct relationship with reliability of dynamic random access memory (DRAM) devices.
Furthermore, the DRAM devices use a cell having a horizontal-type channel. FIG. 1 illustrates a cross-sectional view of a conventional cell structure having a horizontal-type channel. The cell structure having the horizontal-type cell will be referred to as a horizontal channel cell.
As shown in FIG. 1, a plurality of gate lines, each formed by sequentially stacking a gate oxide layer 112, a gate oxide layer 113, and a gate hard mask 114 are formed over a substrate 111. A plurality of gate spacers 115 are formed on sidewalls of the gate lines, and a plurality of source/drain regions 116A and 116B are formed in the substrate 111 adjacent to the gate lines. A bit line BL is connected to the source/drain region 116A and a plurality of storage nodes SN are connected to the source/drain regions 116B.
In the horizontal channel cell shown in FIG. 1, a horizontal-type channel length ‘H-CH’ is formed in the horizontal direction beneath the gate electrode 113.
However, in the DRAM devices using the horizontal-type cells with a gate width of 100 nm or lower, a cell size becomes smaller and a channel length of the cell becomes shorter. Accordingly, a refresh property of the DRAM devices gets degraded, and a gate width becomes smaller. As a result, an operation voltage of the cell can be difficult to control and cell current reduces.